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| STLC2410B BLUETOOTH(R) BASEBAND 1 FEATURES Bluetooth(R) V1.1 specification compliant Point-to-point, point-to-multi-point (up to 7 slaves) and scatternet capability Asynchronous Connection-Less (ACL) link support giving data rates up to 721kbps Synchronous Connection-Oriented (SCO) link Standard BlueRF bus interface ARM7TDMI CPU - 32-bit Core - Run from 13MHz external clock - Support of 32 kHz crystal for low power mode Memory organization - 64KByte on-chip RAM - 4KByte on-chip boot ROM - Programmable external memory interface (EMI) - 8-bit or 16-bit external data bus - Up to 3 programmable chip-select signals - Hold-acknowledge bus arbitration support HW support for all packet types - ACL: DM1, 3, 5 and DH1, 3, 5 - SCO: HV1, 2, 3 and DV1 Communication interfaces - Serial Synchronous Interface - Two enhanced 16550 UART's with 128 byte fifo depth - 12Mbps USB interface - Fast master I2C bus interface - Multi slot PCM interface - 16 programmable GPIO - 2 external interrupts and various interrupt possibilities through other interfaces Ciphering support for up to 128-bit key Receiver Signal Strenght Indication (RSSI) support for power-controlled links Separate control for external power amplifier (PA) for power class1 support. Software support - Low level (up to HCI) stack or embedded stack with profiles - Support of UART and USB HCI transport layers Idle and power down modes - Ultra low power in idle mode - Low standby current TFBGA132 (8x8x1.2mm) ORDERING NUMBER: STLC2410B Temperature range: -40 to +85 C Extended temperature range Compliant to automotive specification AEC-Q100 1.1 Applications Features Typical applications in which the STLC2410B can be used are: Portable computers, PDA Modems Handheld data transfer devices Cameras Computer peripherals Other type of devices that require the wireless communication provided by Bluetooth(R) Cable replacement 2 DESCRIPTION The STLC2410B offers a compact and complete solution for short-range wireless connectivity. It incorporates all the lower layer functions of the Bluetooth(R) protocol. The microcontroller allows the support of all data packets of Bluetooth(R) in addition to voice. The embedded controller can be used to run the Bluetooth(R) protocol and application layers if required. The software is located in an external memory accessed through the external memory interface. 1/20 January 2004 Rev. 2.0 STLC2410B 3 QUICK REFERENCE DATA 3.1 Absolute Maximum Ratings Operation of the device beyond these conditions is not guaranteed. Sustained exposure to these limits will adversely affect device reliability Table 1. Absolute Maximum Ratings Symbol VDD VDDIO VIN Tamb Tstg Tlead Supply voltage core Supply voltage I/O input voltage on any digital pin Operating ambient temperature Storage temperature Lead temperature < 10s VSS - 0.5 -40 -65 Conditions Min VSS - 0.5 Max 2.5 4 VDDIO + 0.3 +85 +150 +240 Unit V V V C C C 3.2 Operating Ranges Operating ranges define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied. Table 2. Operating Ranges Symbol VDD VDDIO Tamb Conditions Supply voltage digital core and emi pads Supply voltage digital IO Operating ambient temperature Min 1.55 2.7 -40 Typ 1.8 3.3 Max 1.95 3.6 +85 Unit V V C 3.3 I/O specifications Depending on the interface, the I/O voltage is typical 1.8V (interface to the flash memory) or typical 3.3V (all the other interfaces). These I/Os comply to the EIA/JEDEC standard JESD8-B. 3.3.1 Specifications for 3.3V I/Os Table 3. LVTTL DC Input Specification (3V Table 4. LVTTL DC Output Specification (3V High level output voltage Ioh =-X mA Note 1 : X is the source/sink current under worst case conditions according to the drive capability. (See table 8, pad information for value of X). 2/20 STLC2410B 3.3.2 Specifications for 1.8V I/Os Table 5. DC Input Specification (1.55V Table 6. DC Output Specification (1.55V Note 1 : X is the source/sink current under worst case conditions according to the drive capability. (See table 8, pad information for value of X). 3.4 Current Consumption Table 7. Typical power consumption of the STLC2410B and External Flash using UART (VDD = VDD Flash = PLLVDD = 1.8V, VDDIO = 3.3V) Core STLC2410B State Slave Standby (no low power mode) Standby (low power mode enabled) ACL connection (no transmission) ACL connection (data transmission) SCO connection (no codec connected) Inquiry and Page scan (low power mode enabled) Low Power mode (32 kHz crystal) 5.10 0.94 7.60 7.90 8.70 127 20 Master 5.10 0.94 6.99 7.20 7.90 n.a. 20 0.13 0.13 0.13 0.13 0.14 5 0 mA mA mA mA mA A A IO Unit 3/20 STLC2410B Figure 1. Block Diagram and Electrical Schematic JTAG VDD 100nF 5 INTERRUPT CONTROLLER PCM 4 2 PCM EXT._INT1/2 VDDIO 100nF USB 2 USB I2C VDDIO 100nF ARM7 TDMI 2 I2C APB BRIDGE SPI 4 SPI RF BUS 13 RADIO I/F BLUETOOTH(R) CORE D M A TIMER GPIO 16 GPIO(O..15) RAM START DETECT UART 8 UART2 (*) 22pF LPOCLKP Y2 32KHz SYSTEM CONTROL LPOCLKN VDD VDDPLL 4 XIN BOOT WAIT RD/WR 3 CSN(0..2) EMI 20 16 D02TL550 LPO BOOT ROM UART FIFO UART 2 UART1 22pF 2 RESET SYS_CLK_REQ VDD 100nF 100nF ADDR(0..19) DATA(0..15) (*) If a low-power clock is available, it can be connected to the LPOCLKP pin in stead of using a crystal 4/20 STLC2410B 4 PINOUT Figure 2. Pinout (Bottom view) 14 13 12 11 10 9 8 7 6 5 4 tdi tdo tms 3 ntrst tck 2 test 1 xin A n.c. gpio10 gpio13 n.c. brclk bnden btxd vdd btxen vddio sys_ nreset clk_req B gpio8 vddpll gpio12 gpio15 vssio bmiso bsen vsspll gpio6 gpio7 gpio3 gpio4 gpio5 gpio0 gpio1 gpio2 lpo_ lpo_ boot clk_p clk_n data 14 data 13 data 10 vdd data 15 data 12 data 9 vss wait data 11 vss vdd vdd vss vss bpktctl vssio uart1_ uart1_ i2c_ rxd txd dat C i2c_clk int1 int2 D pcm_ vddio vssio sync E pcm_ clk pcm_a pcm_b F uart2_ usb_ usb_ rxd dp dn G uart2_ uart2_ uart2_ i2 i1 txd H uart2_ uart2_ uart2_ io1 o2 o1 J vss vdd uart2_ io2 K spi_frm vssio vddio csn1 csn2 spi_ txd wrn spi_ clk spi_ rxd rdn P D02TL551 gpio9 gpio11 gpio14 vddio brxd bmosi bdclk bpaen brxen ant_sw L M N data8 data7 data6 data0 addr17 vss addr13 addr10 addr5 addr2 data5 data4 data2 addr19 addr16 vdd addr12 addr9 addr6 addr3 data3 n.c. data1 addr18 addr15 addr14 addr11 addr8 addr7 addr4 addr1 addr0 csn0 4.1 Pin Description and Assignment Table4 : STLC2410B pinlist shows the pinout of STLC2410B; there are 107 digital functional pins and 22 supply pins. The column "PU/PD" shows the pads implementing an internal weak pull-up/down, to fix value if the pin is left open. This can not replace an external pull-up/down. The pads are grouped according to two different power supply values, as shown in column "VDD": - V1 for 3.3 V typical 2.7 - 3.6 V range - V2 for 1.8 V typical 1.55 - 1.95 V range Finally the column "DIR" describes the pin directions: - I for inputs - O for outputs - I/O for input/outputs - O/t for tristate outputs 5/20 STLC2410B Table 8. Pin List Name Pin # Description DIR PU/PD VDD PAD Interface to external memory int1 int2 boot wait rdn wrn csn0 csn1 csn2 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 addr16 addr17 addr18 addr19 data0 data1 data2 data3 data4 data5 D2 D1 G14 H12 P1 N2 P2 M3 N3 P3 P4 M5 N5 P5 M6 N6 P6 P7 N7 M7 P8 N8 M8 P9 P10 N10 M10 P11 N11 M11 P12 N12 P14 N13 N14 External Interrupt used also as external wakeup Second external interrupt Select external boot from EMI or internal from ROM EMI external wait signal (left open) External read External write External chip select bank 0 External chip select bank 1 External chip select bank 2 External address bit 0 External address bit 1 External address bit 2 External address bit 3 External address bit 4 External address bit 5 External address bit 6 External address bit 7 External address bit 8 External address bit 9 External address bit 10 External address bit 11 External address bit 12 External address bit 13 External address bit 14 External address bit 15 External address bit 16 External address bit 17 External address bit 18 External address bit 19 External data bit 0 External data bit 1 External data bit 2 External data bit 3 External data bit 4 External data bit 5 I I I I O O O O O O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O PD PD PD PD PD PD V2 CMOS 1.8V 4mA slew rate control V2 CMOS 1.8V 4mA slew rate control (1) (1) (1) V1 CMOS, 3.3V TTL compatible schmitt trigger CMOS 1.8V V2 PD 6/20 STLC2410B Table 8. Pin List (continued) Name data6 data7 data8 data9 data10 data11 data12 data13 data14 data15 Pin # M12 M13 M14 K13 K14 J12 J13 J14 H14 H13 External data bit 6 External data bit 7 External data bit 8 External data bit 9 External data bit 10 External data bit 11 External data bit 12 External data bit 13 External data bit 14 External data bit 15 Description DIR I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PU/PD PD PD PD PD PD PD PD PD PD PD V2 CMOS 1.8V 4mA slew rate control VDD PAD SPI interface spi_frm spi_clk L3 M1 Synchronous Serial Interface frame sync Synchronous Serial Interface clock I/O I/O V1 CMOS, 3.3V TTL compatible, 2mA tristate slew rate control schmitt trigger CMOS, 3.3V TTL compatible, 2mA slew rate control CMOS, 3.3V TTL compatible schmitt trigger spi_txd M2 Synchronous Serial Interface transmit data O/t V1 spi_rxd N1 Synchronous Serial Interface receive data I (1) V1 UART interface uart1_txd C2 Uart1 transmit data O/t V1 uart1_rxd C3 Uart1 receive data I (2) CMOS, 3.3V TTL compatible, 2mA slew rate control CMOS, 3.3V TTL compatible schmitt trigger CMOS, 3.3V TTL compatible, 2mA slew rate control CMOS, 3.3V TTL compatible, 2mA slew rate control CMOS, 3.3V TTL compatible CMOS, 3.3V TTL compatible, 2mA tristate slew rate control CMOS, 3.3V TTL compatible, 2mA slew rate control V1 uart2_o1 J1 Uart2 modem output O V1 uart2_o2 J2 Uart2 modem output O/t V1 uart2_i1 uart2_i2 uart2_io1 uart2_io2 H2 H3 J3 K1 Uart2 modem input Uart2 modem input Uart2 modem input/output Uart2 modem input/output I I I/O I/O (2) (2) (2) (2) V1 V1 V1 V1 uart2_txd H1 Uart2 transmit data O/t V1 7/20 STLC2410B Table 8. Pin List (continued) Name uart2_rxd Pin # G3 Description Uart2 receive data DIR I PU/PD (2) VDD V1 PAD CMOS, 3.3V TTL compatible I2C interface i2c_dat i2c_clk C1 D3 I2C data pin I2C clock pin I/O I/O (3) (3) V1 V1 CMOS, 3.3V TTL compatible, 2mA tristate slew rate control USB interface usb_dn usb_dp G1 G2 USB - pin USB + pin I/O I/O (1) (1) V1 V1 GPIO interface gpio0 gpio1 gpio2 gpio3 F14 F13 F12 E14 Gpio port 0 Gpio port 1 Gpio port 2 Gpio port 3 I/O I/O I/O I/O PU PU PU PU V1 V1 CMOS, 3.3V TTL compatible, 4mA tristate slew rate control CMOS, 3.3V TTL compatible, 4mA tristate slew rate control schmitt trigger CMOS, 3.3V TTL compatible, 4mA tristate slew rate control gpio4 gpio5 gpio6 gpio7 gpio8 gpio9 gpio10 gpio11 gpio12 gpio13 gpio14 gpio15 E13 E12 D13 D12 C14 A14 B13 A13 C12 B12 A12 C11 Gpio port 4 Gpio port 5 Gpio port 6 Gpio port 7 Gpio port 8 Gpio port 9 Gpio port 10 Gpio port 11 Gpio port 12 Gpio port 13 Gpio port 14 Gpio port 15 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PU PU PU PU PU PU PU PU PU PU PU PU V1 CMOS, 3.3V TTL compatible, 2mA tristate slew rate control V1 CMOS, 3.3V TTL compatible, 2mA tristate slew rate control V1 Clock and test pins xin nreset A1 B2 System clock Reset System clock request I I I/O V1 V1 CMOS, 3.3V TTL compatible schmitt trigger CMOS, 3.3V TTL compatible, 2mA tristate slew rate control sys_clk_req B1 lpo_clk_p lpo_clk_n test G13 G12 A2 Low power oscillator + / Slow clock input Low power oscillator Test mode I O I (1) V2 PD V1 CMOS, 3.3V TTL compatible 8/20 STLC2410B Table 8. Pin List (continued) Name Pin # Description DIR PU/PD VDD PAD JTAG interface ntrst tck A3 B3 JTAG pin JTAG pin I I PD (1) V1 CMOS, 3.3V TTL compatible CMOS, 3.3V TTL compatible schmitt trigger CMOS, 3.3V TTL compatible CMOS, 3.3V TTL compatible, 2mA slew rate control V1 tms tdi tdo C4 A4 B4 JTAG pin JTAG pin JTAG pin (should be left open) I I O/t V1 PCM interface pcm_a pcm_b pcm_sync pcm_clk F2 F1 E1 F3 PCM data PCM data PCM 8kHz sync PCM clock I/O I/O I/O I/O PD PD PD PD V1 V1 PU PU V1 CMOS, 3.3V TTL compatible, 2mA tristate slew rate control CMOS, 3.3V TTL compatible, 2mA tristate slew rate control schmitt trigger Radio interface brclk brxd bmiso bnden bmosi bdclk btxd bsen bpaen brxen btxen bpktctl ant_sw B10 A10 C9 B9 A9 A8 B8 C8 A7 A6 B6 C6 A5 Transmit clock Receive data RF serial interface input data RF serial interface control RF serial interface output data RF serial interface clock Transmit data Synthesizer ON Open PLL Receive ON Transmit ON Packet ON Antenna switch I I I O O O O O O O O O O V1 CMOS, 3.3V TTL compatible, 8mA slew rate control V1 CMOS, 3.3V TTL compatible, 2mA slew rate control (1) (1) V1 CMOS, 3.3V TTL compatible schmitt trigger CMOS, 3.3V TTL compatible V1 (1) Should be strapped to vssio if not used (2) Should be strapped to vddio if not used (3) Should have a 10 kOhm pull-up if not used. 9/20 STLC2410B Table 4. Pin List (continued) Name Pin # Power Supply vsspll D14 vddpll C13 vdd B7 vdd K2 vdd L12 vdd L14 vdd M4 vdd N9 vddio A11 vddio B5 vddio E3 vddio L1 vss C7 vss K3 vss K12 vss L13 vss M9 vss N4 vssio C5 vssio C10 vssio E2 vssio L2 Description PLL ground 1.8V supply for PLL 1.8V Digital supply 1.8V Digital supply 1.8V Digital supply 1.8V Digital supply 1.8V Digital supply 1.8V Digital supply 3.3V I/O's supply 3.3V I/O's supply 3.3V I/O's supply 3.3V I/O's supply Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground I/O's ground I/O's ground I/O's ground I/O's ground 10/20 STLC2410B 5 FUNCTIONAL DESCRIPTION 5.1 Baseband 5.1.1 Overview The baseband is fully compliant with the Bluetooth(R) specification 1.1, including: - 7 slaves support. - Asynchronous Connection-Less (ACL) link support giving data rates up to 721kb per second. - Synchronous Connection-Oriented (SCO) link with support for 1 voice channel over the air interface. - HW support for all packet types: - ACL: DM1, 3, 5 and DH1, 3, 5. - SCO: HV1, 2, 3, and DV1. - Support for three PCM channels in the PCM interface. - Architecture gives ultra-low power consumption. - Ciphering support for up to 128-bit, configurable by software. - Receiver Signal Strenght Indication (RSSI) support for power-controlled links. - Flexible voice formats to Host and over air (CVSD, PCM 16/8-bit, A-law, -law). - High quality filtering of voice packets enabling excellent audio quality. - Point-to-multipoint support. - Scatternet support, communication between two simultaneously running piconets. - Full Bluetooth(R) software stack available. - Low level link controller. - Specific external power amplifier (PA) control for class1 support. - Extended wake-up and interrupt functionality for HID support. 5.1.2 Processor and memory - ARM7TDMI. - 64Kbyte of static RAM. - 4Kbyte of metal programmable ROM - Extension of the ARM Bus to handle external program FLASH or RAM or dedicated peripherals. - Data bus in byte or half word format (8-bit or 16-bit). - Address bus 20-bit wide to support 1 Mbyte within each bank. - Direct Support for 3 external devices. - Access to slow peripherals. 11/20 STLC2410B 6 GENERAL SPECIFICATION 6.1 SYSTEM CLOCK The STLC2410B works with a single clock provided on the XIN pin. The value of this external clock should be 13MHz 20ppm (overall). 6.1.1 SLOW CLOCK The slow clock is used by the baseband as reference clock during the low power modes. Compared to the 13MHz clock, the slow clock only requires an accuracy of 250ppm (overall). Several options are foreseen in order to adjust the STLC2410B behaviour according to the features of the radio used: - if the system clock (e.g. 13MHz) is not provided at all times (power consumption saving) and no slow clock is provided by the system, a 32 kHz crystal must be used by the STLC2410B (default mode). - if the system clock (e.g. 13MHz) is not provided at all times (power consumption saving) and the system provides a slow clock at 32kHz or 3.2kHz, this signal in simply connected to the STLC2410B (lpo_clk_p). - if the system clock (e.g. 13MHz) is provided at all times, the STLC2410B generates from the 13MHz reference clock an internal 32kHz clock. This mode is not an optimized mode for power consumption. 6.2 BOOT PROCEDURE The boot code instructions are the first that ARM7TDMI executes after an HW reset. All the internal device's registers are set to their default value. There are 2 types of boot: - external flash boot. When boot pin is set to 1 (connected to VDD), the STLC2410B boots on its external memory which is normally a flash memory. - UART download boot from ROM. When boot pin is set to 0 (connected to GND), the STLC2410B boots on its internal ROM (needed to download the new firmware). When booting on the internal ROM, the STLC2410B will monitor the UART interface for approximately 1.4 second. If there is no request for code downloading during this period, the ROM jumps to external flash. 6.3 CLOCK DETECTION The STLC2410B has a automatic slow clock frequency detection (32kHz, 3.2kHz or none). 6.4 MASTER RESET When the device's reset is held active (NRESET is low), all two uart txd pins (UART1_TXD and UART2_TXD) are driven low. When the NRESET returns high, the device starts to boot. Remark: The device should be held in active reset for minimum 20ms in order to guarantee a complete reset of the device. 6.5 INTERRUPTS/WAKE-UP The external pins int1 and int2, and up to 8 GPIOs can be used both as external interrupt source and as wake-up source. In addition the chip can be woken-up by USB or Uart Rx. 12/20 STLC2410B 7 INTERFACES 7.1 UART Interface The chip contains two enhanced (128-byte FIFO depth, sleep mode, 127 Rx and 128 Tx interrupt tresholds) UARTs named UART1 and UART2 compatible with the standard M16550 UART. For UART1, only Rx and Tx signals are available (mainly used for debug purposes and in test mode). UART2 features: - standard HCI UART transport layer: - all HCI commands as described in the Bluetooth(R) specification 1.1 - ST specific HCI command (check STLC2410B Software Interface document for more information) - RXD, TXD, CTS, RTS on permanent external pins - 128-byte FIFOs, for transmit and for receive - Default configuration: 57.6 kbits/s - Specific HCI command to change to the following baud rates: Table 9. List of supported baud rates Baud rate - 921.6k 460.8 k 230.4 k 153.6 k 115.2 k 76.8 k 57.6 k (default) 38.4 k 28.8 k 19.2 k 14.4 k 9600 7200 4800 2400 1800 1200 900 600 300 7.2 Synchronous Serial Interface The Synchronous Serial Interface is a flexible module that supports full-duplex and half-duplex synchronous communications with external devices in Master and Slave mode. It allows the STLC2410B to communicate with peripheral devices. The Synchronous Serial Interface is also capable of inter processor communications in a multiple-master system. This interface is flexible enough to interface directly with numerous standard product peripherals. This Synchronous Serial Interface peripheral features: - - - - - - - - - full duplex, four-wire synchronous transfers. Microwire half duplex transfer using 8-bit control message programmable clock polarity and phase. transmit data pin tri state able when not transmitting Master or Slave operation Programmable clock bit rate up to XIN/4 Programmable data frame from 4 bits to 16 bits. Independent transmit and receive 16 words FIFO. Internal loopback 7.3 I2C Interface The I2C port is used both to connect to an external E2PROM and to access I2C peripherals like the STw5094 Codec. The I2C implemented in the STLC2410B is a master I2C, it has the full control of the I2C bus at all time. I2C slave functionality is not supported, so any other I2C attached to the I2C bus must be slave, otherwise bus contention will occur. 13/20 STLC2410B Figure 3. I2C BUS master flow diagram IDLE STA SEND START SEND ADDR STA RECEIVE ACKNOWLEDGE RX TX TX DATA RX DATA RECEIVE DATA SEND DATA SEND ACKNOWLEDGE RX STA STP STP RECEIVE ACKNOWLEDGE STA TX SEND STOP D02TL554 7.4 USB Interface The USB interface is compliant with the USB 2.0 full speed specification. Max throughput on the USB interface is 12 Mbit/s. Figure 4 gives an overview of the main components needed for supporting the USB interface, as specified in the Bluetooth(R) Core Specification ( Part H:2). For clarity, the serial interface (including the UART Transport Layer) is also shown. 14/20 STLC2410B Figure 4. USB Interface HCI USB TRANSPORT LAYER UART TRANSPORT LAYER USB DEVICE REGISTERS FIFOs USB DRIVER SERIAL DRIVER UART DEVICE REGISTERS FIFOs IRQ RTOS IRQ STLC2410B HW D02TL555 The USB device registers and FIFOs are memory mapped. The USB Driver will use these registers to access the USB interface. The equivalent exists for the HCI communication over UART. For transmission to the host, the USB & Serial Drivers interface with the HW via a set of registers and FIFOs, while in the other direction, the hardware may trigger the Drivers through a set of interrupts (identified by the RTOS, and directed to the appropriate Driver routines). 7.5 JTAG Interface The JTAG interface is compliant with the JTAG IEEE Std 1149.1. Its allows both the boundary scan of the digital pins and the debug of the ARM7TDMI application when connected with the standard ARM7 development tools. 7.6 RF Interface The STLC2410B radio interface is compatible to BlueRF (unidirectional RxMode2 for data and unidirectional serial interface for control). 7.7 PCM voice interface The voice interface is a direct PCM interface to connect to a standard CODEC (e.g. STw5093 or STw5094) including internal decimator and interpolator filters. The data can be linear PCM (13-16bit), Law (8bit) or A-Law (8bit). By default the codec interface is configured as master. The encoding on the air interface is programmable to be CVSD, A-Law or -Law. The PCM block is able to manage the PCM bus with up to 3 timeslots. PCM clock and data are in master mode available at 2 MHz or at 2.048 MHz to allow interfacing of standard codecs. 15/20 STLC2410B The four signals of the PCM interface are: - PCM_CLK : PCM clock - PCM_SYNC : PCM 8kHz sync - PCM_A : PCM data - PCM_B : PCM data Directions of PCM_A and PCM_B are software configurable. Figure 5. PCM (A-law, -law) standard mode 0 PCM_CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PCM_SYNC PCM_A B B PCM_B B 125s B D02TL558 Figure 6. Linear mode 0 PCM_CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PCM_SYNC PCM_A PCM_B 125s D02TL559 Table 10. PCM interface timing. Symbol PCM Interface Fpcm_clk Fpcm_sync tWCH tWCL tWSH tSSC tSDC tHCD tDCD Frequency of PCM_CLK (master) Frequency of PCM_SYNC High period of PCM_CLK Low period of PCM_CLK High period of PCM_SYNC Setup time, PCM_SYNC high to PCM_CLK low Setup time, PCM_A/B input valid to PCM_CLK low Hold time, PCM_CLK low to PCM_A/B input invalid Delay time, PCM_CLK high to PCM_A/B output valid 200 200 200 100 100 100 150 2048 8 kHz kHz ns ns ns ns ns ns ns Description Min Typ Max Unit 16/20 STLC2410B Figure 7. PCM interface timing tWCL PCM_CLK tWCH tSSC PCM_SYNC tWSH tSDC tHCD MSB MSB-1 MSB-2 MSB-3 MSB-4 PCM_A/B in tDCD PCM_B/A out MSB MSB-1 MSB-2 MSB-3 MSB-4 D02TL557 8 HCI UART TRANSPORT LAYER The UART Transport Layer is specified by the Bluetooth(R) SIG ( Part H:4), and allows HCI level communication between a host controller (STLC2410B) and a host (e.g. PC), via a RS232 interface. The objective of this HCI UART Transport Layer is to make it possible to use the Bluetooth(R) HCI over a serial interface between two UARTs on the same PCB. The HCI UART Transport Layer assumes that the UART communication is free from line errors. 8.1 UART Settings The HCI UART Transport Layer uses the following settings: - Baud rate: Configurable (Default baud rate: 57.6 kbits/s) - Number of data bits: 8 - Parity bit: no parity - Stop bit: 1 stop bit - Flow control: RTS/CTS - Flow-off response time: 3 ms Flow control with RTS/CTS is used to prevent temporary UART buffer overrun. It should not be used for flow control of HCI, since HCI has its own flow control mechanisms for HCI commands, HCI events and HCI data. If CTS is 1, then the Host/Host Controller is allowed to send. If CTS is 0, then the Host/Host Controller is not allowed to send. The flow-off response time defines the maximum time from setting RTS to 0 until the byte flow actually stops. The signals should be connected in a null-modem fashion; i.e. the local TXD should be connected to the remote RXD and the local RTS should be connected to the remote CTS and vice versa. Figure 8. UART Transport Layer BLUETHOOTH HOST BLUETHOOTH HCI BLUETHOOTH HOST CONTROLLER HCI UART TRANSPORT LAYER D02TL556 17/20 STLC2410B 9 HCI USB TRANSPORT LAYER The USB Transport Layer has been specified by the Bluetooth(R) SIG (Part H:2), and allows HCI level communication between a host controller (STLC2410B) and a host (e.g. PC), via a USB interface. The USB Transport Layer is completely implemented in SW. It accepts HCI messages from the HCI Layer, prepares it for transmission over a USB bus, and sends it to the USB Driver. It reassembles the HCI messages from USB data received from the USB Driver, and sends these messages to the HCI Layer. The Transport Layer does not interprete the contents (payload) of the HCI messages; it only examines the header. 10 POWER CLASS1 SUPPORT The chip can control an external power amplifier (PA). Several signals are duplicated on GPIOs for this purpose in order to avoid digital/analog noise loops in the radio. The Class1_En register enables the alternate functions of GPIO[15:6] to generate the signals for driving an external PA in a Bluetooth(R) power class1 application. Every bit enables a dedicated signal on a GPIO pin, as described in Table 11 : Power Class 1 functionality. Table 11. Power Class 1 functionality Class1_En bit rxon not rxon PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 involved GPIO gpio[6] gpio[7] gpio[8] gpio[9] gpio[10] gpio[11] gpio[12] gpio[13] gpio[14] gpio[15] description (when class1_En bit = `1') outputs a copy of rx_on pin to switch LNA/RF switch on/off outputs an inverted copy of rx_on pin to switch LNA/RF switch on/off Bit 0 of the PA value for the current connection Bit 1 of the PA value for the current connection Bit 2 of the PA value for the current connection Bit 3 of the PA value for the current connection Bit 4 of the PA value for the current connection Bit 5 of the PA value for the current connection Bit 6 of the PA value for the current connection Bit 7 of the PA value for the current connection rx_on is the same as the rx_on output pin. Not rx_on is the inverted signal, in order to save components on the application board. PA7 to PA0 are the power amplifier control lines. They are managed, on a connection basis, by the baseband core. The Power Level programmed for a certain Bluetooth(R) connection is manged by the firmware, as specified in the Bluetooth(R) SIG spec. 18/20 STLC2410B mm DIM. MIN. A A1 A2 b D D1 E E1 e f ddd 0.450 0.600 7.850 0.250 7.850 1.010 0.150 0.820 0.300 8.000 6.500 8.000 6.500 0.500 0.750 0.550 0.900 0.080 0.018 0.024 8.150 0.310 0.350 8.150 0.010 0.310 TYP. MAX. 1.200 MIN. 0.040 0.006 inch TYP. MAX. 0.047 OUTLINE AND MECHANICAL DATA 0.032 0.012 0.315 0.256 0.315 0.256 0.020 0.029 0.022 0.035 0.003 0.321 0.014 0.321 Body: 8 x 8 x 1.20mm TFBGA132 Fine Pitch Ball Grid Array 7146828 A 19/20 STLC2410B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. The BLUETOOTH(R) word mark and logos are owned by the Bluetooth SIG, Inc. and any use of such marks by STMicroelectronics is under license. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 20/20 |
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